Page mode memories have been developed to increase the amount of memory that is available for use in a system when the number of address lines is limited. U.S. Pat. No. 4,368,515, Nielsen, describes such a purpose. In conventional techniques the number of memory locations which can be addressed when the number of address bits is n, is 2 to the n power. For the case of n=12, the maximum number of memory locations which can be accessed is 4096. The technique described in the above patent doubles the addressable memory space by designating a particular address as determining which half of the memory will provide the data in response to the addresses until a second predetermined address is received causing the other half of the memory to provide the data. In such a case, each half represents a page or bank. Using more than two pages in doubling the amount of memory adds flexibility. At any given time, whether 2 pages or more than two pages, only one half of the memory is accessible. But with only two pages, accessible memory is always in one of the two specific pages. If, however, there are eight pages, any four could be accessible at a given time i.e., the particular half of the memory which is accessible could be made up of any four of the pages. This adds to user flexibility.
A programmable system, however, is required to implement the flexibility of choosing which four pages are to form the one half of accessible memory. In so doing there is then a problem of address skew causing false programming. The addresses may change at somewhat different times so that during such a transition one of the programming addresses may accidentally be obtained, thereby unknowingly changing the state of the programmed circuit which selects the accessible page or pages. Obviously, it is of critical importance to know which pages are accessible at any given time. An additional problem in this regard relates to coming out of a programming cycle. The signals which contain the information to be stored may change too quickly for the comparatively complicated logic circuitry associated with controlling the storage to respond to such transition.